The present invention relates generally to flash memory cell devices and more specifically, to improvements in pre-charge reading methods for reading a charge previously stored in a dual bit dielectric memory cell structure.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate disburses across the semi conductive gate and has the effect of increasing the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a xe2x80x9creadxe2x80x9d of the memory cell, the programmed, or non-programmed, state of the memory cell can be detected by detecting the magnitude of the current flowing between the source and drain at a predetermined control gate voltage.
More recently dielectric memory cell structures have been developed. A conventional array of dielectric memory cells 10a-10f is shown in cross section in FIG. 1. Each dielectric memory cell is characterized by a vertical stack of an insulating tunnel layer 18, a charge trapping dielectric layer 22, an insulating top oxide layer 24, and a polysilicon control gate 20 positioned on top of a crystalline silicon substrate 15. Each polysilicon control gate 20 may be a portion of a polysilicon word line extending over all cells 10a-10f such that all of the control gates 20a-20g are electrically coupled.
Within the substrate 15 is a channel region 12 associated with each memory cell 10 that is positioned below the vertical stack. One of a-plurality of bit line diffusions 26a-26g separate each channel region 12 from an adjacent channel region 12. The bit line diffusions 26 form the source region and drain region of each cell 10. This particular structure of a silicon channel region 22, tunnel oxide 12, nitride 14, top oxide 16, and polysilicon control gate 18 is often referred to as a SONOS device.
Similar to the floating gate device, the SONOS memory cell 10 is programmed by inducing hot electron injection from the channel region 12 to the charge trapping dielectric layer 22, such as silicon nitride, to create a non volatile negative charge within charge traps existing in the nitride layer 22. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate 20. The high voltage on the control gate 20 inverts the channel region 12 while the drain-to-source bias accelerates electrons towards the drain region. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Sixe2x80x94SiO2 energy barrier between the channel region 12 and the tunnel oxide 18. While the electrons are accelerated towards the drain region, those electrons which collide with the crystalline lattice are re-directed towards the Sixe2x80x94SiO2 interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region that is close to the drain region. For example, a charge can be stored in a drain bit charge storage region 16b of memory cell 10b. The bit line 26b operates as the source region and bit line 26c operates as the drain region. A high voltage may be applied to the channel region 20b and the drain region 26c while the source region 26b is grounded.
Similarly, a source-to-drain bias may be applied along with a high positive voltage on the control gate to inject hot electrons into a source charge storage region that is close to the source region. For example, grounding the drain region 26c in the presence of a high voltage on the gate 20b and the source region 26b may be used to inject electrons into the source bit charge storage region 14b. 
As such, the SONOS device can be used to store two bits of data, one in each of the source charge storage region 14 (referred to as the source bit) and the charge storage region 16 (referred to as the drain bit).
Due to the fact that the charge stored in the storage region 14 only increases the threshold voltage in the portion of the channel region 12 beneath the storage region 14 and the charge stored in the storage region 16 only increases the threshold voltage in the portion of the channel region 16 beneath the storage region 16, each of the source bit and the drain bit can be read independently by detecting channel inversion in the region of the channel region 12 between each of the storage region 14 and the storage region 16. To xe2x80x9creadxe2x80x9d the drain bit, the drain region is grounded while a voltage is applied to the source region and a slightly higher voltage is applied to the gate 20. As such, the portion of the channel region 12 near the source/channel junction will not invert (because the gate 20 voltage with respect to the source region voltage is insufficient to invert the channel) and current flow at the drain/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the drain bit.
Similarly, to xe2x80x9creadxe2x80x9d the source bit, the source region is grounded while a voltage is applied to the drain region and a slightly higher voltage is applied to the gate 20. As such, the portion of the channel region 12 near the drain/channel junction will not invert and current flow at the source/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the source bit.
In a typical flash memory array, the row and column structure creates problems when reading a selected cell. Each memory cell within a column shares a common source bit line and drain bit line with other memory cells within the column. As such, if other cells within the column leak current between the source bit line and the drain bit line, the current flow may not accurately represent only the current drawn from grounded bit line through the channel region of the selected cell. The current may also represent leakage through other cells within the column and therefore the state of the selected cell may be mis-read. As memory array applications demand smaller memory cells structures, the short channel effects of the smaller cell structure increases the likelihood of a punch-through phenomena for the non-selected cells within a selected column.
Further, each memory cell within a row shares a common word line with other cells within the row. As such, leakage through the channel region of one of the cells adjacent to the selected cell in the same row (e.g. one of the cells that shares common bit line with the selected cell) may also cause the state of the selected cell to be mis-read.
What is needed is an improved method for reading a dual bit dielectric memory cell that does not suffer the disadvantages of the known methods.
A first aspect of the present invention is to provide a method of detecting a charge stored on a source charge storage region of a selected dual bit dielectric memory cell within an array of dual bit dielectric memory cells. The array comprises columns of alternating parallel bit lines, of a first conductivity semiconductor, and channel regions, of an opposite conductivity semiconductor. The bit lines form a source and a drain for each cell within a column. A plurality of parallel word lines, arranged in rows that are perpendicular to the columns, form a gate for each cell within the row.
The method of detecting the charge stored on a source charge storage region comprises applying a source voltage to a first bit line that forms a source junction with a channel region of the selected memory cell, applying a positive drain voltage to a second bit line that forms a drain junction with the channel region, applying a positive read voltage to the selected one of the word lines that forms a gate of the selected memory cell, applying a bias voltage to the non-selected word lines (e.g the word lines other than the selected word line), and detecting current flow at the second bit line.
The source voltage may be ground or a small positive voltage on the order of 0.0 volt to 1.0 volt, the read voltage on the gate may be greater than the source voltagexe2x80x94on the order of 10 volts, and the bias voltage may be a negative voltage. More specifically, the bias voltage may be a negative voltage between xe2x88x920.1 volt and xe2x88x922.0 volt; or for a more narrow range, between xe2x88x920.1 volt and xe2x88x920.5 volt; or for a more narrow range yet, between xe2x88x920.1 volt and xe2x88x920.2 volt.
The above described steps are intended to prevent punch-through leakage of current through non-selected memory cells that share the same column as the selected memory cell within the array. It is also envisioned that the above described steps may be combined with the following steps intended to prevent leakage of current through non-selected cells that share the same row as the selected cell and are adjacent to the selected cell (e.g. sharing a bit line). Such steps include isolating, or floating, a third bit line such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line (the third bit line being the next bit line to the right of the second bit line and separated from the second bit line by only the second channel region and the channel region being to the right of the third bit line) and applying a positive bias voltage to a pre-charge bit line. The pre-charge bit line may be a fourth bit line that is the next bit line to the right of the third bit line and separated from the third bit line by only a third channel region.
A second aspect of the present invention is to provide an array of dual bit dielectric memory cells. The array comprises: a) a first bit line of a first conductivity semiconductor forming a source region for each of a plurality of memory cells within a column of memory cells within the array; b) a first channel region of an opposite conductivity semiconductor forming a channel region for each of the plurality of memory cells within the column; c) a second bit line of the first conductivity semiconductor forming a drain region for each of the plurality of memory cells within the column, the second bit line separated from the first bit line by only the first channel region; d) a selected word line positioned over the channel region and forming a gate for each for a plurality of memory cells within a row of memory cells within the array; e) a plurality of non-selected word lines, each parallel to the selected word line and each forming a gate for each of a plurality of memory cells within a row of non-selected memory cells within the array; f) a word line control circuit; g) a bit line control circuit; and h) a current sensor circuit for detecting the state of the stored charge in a source charge storage region by detecting current flow at the second bit line.
The word line control circuit provides for applying a positive read voltagexe2x80x94on the order of 10 voltsxe2x80x94to the selected word line and a bias voltage to the non-selected word lines. The bias voltage may be a negative voltage. More specifically, the bias voltage may be a negative voltage between xe2x88x920.1 volt and xe2x88x922.0 volt; or for a more narrow range, between xe2x88x920.1 volt and xe2x88x920.5 volt; or for a more narrow range yet, between xe2x88x920.1 volt and xe2x88x920.2 volt.
The bit line control circuit provides for applying a source voltage to the source bit line and a positive drain voltage to the drain bit line. The source voltage may be ground or may be a small positive voltage between 0.0 volts and 1.0 volts.
The array may further comprise: i) a second channel region adjacent to the second bit line and forming a junction with the second bit line; j) a third bit line adjacent to the second channel region and forming a junction with the second channel region, the third bit line separated from the second bit line by only the second channel region; k) a third channel region adjacent to the third bit line and forming a junction with the third bit line; and l) a pre-charge bit line to the right of the third channel region which may be a fourth bit line that forms a junction with the third channel region. In which case, the bit line control circuit may further provide for: i) isolating the third bit line such that its potential is effected only by its junctions with the a second channel region and the third channel region; and ii) applying a positive voltage to the pre-charge bit line.
For a better understanding of the present invention, together with other and further aspects thereof, reference is made to the following description, taken in conjunction with the accompanying drawings. The scope of the invention is set forth in the appended clams.